index - Equipe Secure and Safe Hardware

 

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Mots clés

Computational modeling Countermeasures Machine learning Fault injection Hardware Formal proof GSM Signal processing algorithms Asynchronous Field Programmable Gates Array FPGA Differential Power Analysis DPA Estimation Aging Side-Channel Attacks Fault injection attack Robustness Lightweight cryptography Linearity Electromagnetic Sensors Protocols Switches Gem5 Security Internet of Things Mutual Information Analysis MIA Side-Channel Analysis Magnetic tunneling Formal methods ASIC Power-constant logic Masking countermeasure Filtering Side-channel attacks SCA STT-MRAM Random access memory FDSOI Differential power analysis DPA Hardware security Writing Side-channel attack Memory Controller Countermeasure Training SCA Temperature sensors Reliability Neural networks Side-channel analysis EMFI Security and privacy Cryptography Convolution Intrusion detection Security services TRNG Defect modeling Application-specific VLSI designs Resistance Power demand Side-Channel Analysis SCA Simulation 3G mobile communication Receivers Logic gates Authentication Process variation Dual-rail with Precharge Logic DPL Energy consumption OCaml PUF Confusion coefficient Transistors Routing Side-channel attacks Elliptic curve cryptography Costs Randomness Reverse engineering Fault attacks AES Coq SoC Dynamic range Information leakage MRAM CRT Masking Loop PUF Field programmable gate arrays Spin transfer torque FPGA RSA Voltage DRAM Circuit faults Image processing Magnetic tunnel junction Reverse-engineering CPA

 

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433

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42 %

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